Circuits that swtich between a sample mode and a hold mode are used widely. During the sample mode, such a sample and hold (S/H) circuit tracks an analog input voltage. During the hold mode, the S/H circuit stores the value of the input voltage that existed just before the circuit switched from sample to hold.
An important objective in designing an S/H circuit is to minimize the offset voltage error in the circuit output signal provided during hold. One way of doing this is to arrange the circuit in such a manner that the total voltage offset occurring during sample is of largely the same magnitude but opposite sign to that occurring during hold so that the offsets cancel. This technique is referred to as auto-zeroing.
U.S. Pat. Nos. 3,696,305, 4,119,960, and 4,302,689 disclose auto-zero S/H circuits. Each of these circuits contains an operational amplifier (hereafter "op amp") whose output voltage slews through at least the value of the analog input voltage when the circuit switches from sample to hold. Becuase the circuit has to settle before a steady-state value is reached for the output voltage, the acquisition time in the hold mode is high.
F. Gasparik, "An Autozeroing Sample and Hold IC," 1980 IEEE Int'l Solid-State Circs. Conf., Dig., Tech. Paps., February 1980, pgs. 132-133, describes an S/H circuit that achieves excellent offset voltage cancellation with less slewing than in the foregoing patents. A disadvantage of the Gasparik circuit is that it has to settle twice during a sample and hold operation. This substantially increases the total acquisition time.